B
    `V                 @   s   d Z ddlZddlmZmZmZmZmZmZ ddl	m
Z
mZmZmZmZmZmZmZ dddgZG dd deZG d	d deZG d
d deZdS )z
    pygments.lexers.hdl
    ~~~~~~~~~~~~~~~~~~~

    Lexers for hardware descriptor languages.

    :copyright: Copyright 2006-2021 by the Pygments team, see AUTHORS.
    :license: BSD, see LICENSE for details.
    N)
RegexLexerbygroupsincludeusingthiswords)TextCommentOperatorKeywordNameStringNumberPunctuationVerilogLexerSystemVerilogLexer	VhdlLexerc               @   s  e Zd ZdZdZddgZdgZdgZdZde	j
dfd	efd
efdefde	jfde	jfdefdedfdejfdejfdejfdejfdejfdejfdejfdefdejfdefdefdejfdeeejefdeeejedfed d!d"efed#d$d!d%e	j
fed&d'd!d%ejfed(d!d"ejfd)ej fd*efd+efgd,ed-fd.ej!fd/efdefd0efgd1e	j
fd2e	jfd3e	jd-fd4e	j
fd5e	j
fd	e	j
d-fgd6ejd-fgd7Z"d8d9 Z#d:S );r   zZ
    For verilog source code with preprocessor directives.

    .. versionadded:: 1.4
    Zverilogvz*.vztext/x-verilogz(?:\s|//.*?\n|/[*].*?[*]/)+z^\s*`definemacroz\nz\s+z\\\nz/(\\\n)?/(\n|(.|\n)*?[^\\]\n)z/(\\\n)?[*](.|\n)*?[*](\\\n)?/z[{}#@]zL?"stringz4L?'(\\.|\\[0-7]{1,3}|\\x[a-fA-F0-9]{1,2}|[^\\\'\n])'z%(\d+\.\d*|\.\d+|\d+)[eE][+-]?\d+[lL]?z(\d+\.\d*|\.\d+|\d+[fF])[fF]?z([0-9]+)|(\'h)[0-9a-fA-F]+z([0-9]+)|(\'b)[01]+z([0-9]+)|(\'d)[0-9]+z([0-9]+)|(\'o)[0-7]+z\'[01xz]z\d+[Ll]?z[~!%^&*+=|?:<>/-]z[()\[\],.;\']z`[a-zA-Z_]\w*z^(\s*)(package)(\s+)z^(\s*)(import)(\s+)import)qalwaysalways_comb	always_ffalways_latchandassign	automaticbeginbreakbufbufif0bufif1casecasexcasezcmosconstcontinuedeassigndefaultdefparamdisabledoedgeelseendendcaseendfunctionendgenerate	endmodule
endpackageendprimitive
endspecifyendtableendtaskenumeventfinalforforceforeverforkfunctiongenerategenvarhighz0highz1ifinitialinoutinputintegerjoinlarge
localparammacromodulemediummodulenandnegedgenmosnornotnotif0notif1oroutputpacked	parameterpmosposedge	primitivepull0pull1pulldownpulluprcmosrefreleaserepeatreturnrnmosrpmosrtranrtranif0rtranif1scalaredsignedsmallspecify	specparamZstrengthr   strong0strong1structtabletasktrantranif0tranif1typetypedefunsignedvarvectoredvoidwaitweak0weak1whilexnorxorz\b)suffix)Z
accelerateZautoexpand_vectornetsZ
celldefineZdefault_nettyper/   elsifZendcelldefineendifZ
endprotectZendprotectedZexpand_vectornetsZifdefZifndefr   ZnoaccelerateZnoexpand_vectornetsZnoremove_gatenamesZnoremove_netnamesZnounconnected_driveZprotect	protectedZremove_gatenamesZremove_netnamesZresetallZ	timescaleZunconnected_driveZundef`)prefixr   )4bitsZ
bitstorealZbitstoshortrealZcountdriversZdisplayZfcloseZfdisplayfinishfloorZfmonitorZfopenZfstrobeZfwriteZ
getpatternhistoryZincsaverI   ZitorkeylistlogZmonitorZ
monitoroffZ	monitoronZnokeynologZprinttimescalerandomZreadmembZreadmemhrealtimeZ
realtobitsresetZreset_countZreset_valueZrestartZrtoisaveZscaleZscopeZshortrealtobitsZ
showscopesZshowvariablesZshowvarsZ	sreadmembZ	sreadmemhZstimestopZstrobetimeZ
timeformatwritez\$)byteshortintintlongintrJ   r   bitlogicregsupply0supply1tritriandtriortri0tri1trireguwirewirewandZworshortrealrealr   z[a-zA-Z_]\w*:(?!:)z\$?[a-zA-Z_]\w*z\\(\S+)"z#popz/\\([\\abfnrtv"\']|x[a-fA-F0-9]{2,4}|[0-7]{1,3})z	[^\\"\n]+z\\z[^/\n]+z/[*](.|\n)*?[*]/z//.*?\n/z	(?<=\\)\nz	[\w:]+\*?)rootr   r   r   c             C   s8   d}d| kr|d7 }d| kr$|d7 }d| kr4|d7 }|S )z`Verilog code will use one of reg/wire/assign for sure, and that
        is not common elsewhere.r   r   g?r   r    )textresultr   r   [/home/kop/projects/devel/pgwui/test_venv/lib/python3.7/site-packages/pygments/lexers/hdl.pyanalyse_text   s    zVerilogLexer.analyse_textN)$__name__
__module____qualname____doc__namealiases	filenames	mimetypes_wsr	   Preprocr   Single	Multiliner   r   Charr   FloatHexBinIntegerOctr
   r   Constantr   r   	Namespacer   BuiltinTypeLabelEscapetokensr   r   r   r   r   r      sz   

c            "   @   s  e Zd ZdZdZddgZddgZdgZdZde	j
d	fd
eeejefdeeejedfdefdefdefde	jfde	jfdefdedfdejfdejfdejfdejfdejfdejfdejfdefdejfdefedd d!ejfd"efd#ejfed$d d!efd%eejeej fd&eejeej fd'eejeeeej fed(d d!ej!fed)d d!e	j
fed*d d!ej"fd+ej#fd,efd-efg!d.ed/fd0ej$fd1efdefd2efgd3e	j
fd4e	jfd5e	jd/fd6e	j
fd7e	j
fde	j
d/fgd8ejd/fgd9Z%d:S );r   z
    Extends verilog lexer to recognise all SystemVerilog keywords from IEEE
    1800-2009 standard.

    .. versionadded:: 1.5
    Zsystemverilogsvz*.svz*.svhztext/x-systemverilogz(?:\s|//.*?\n|/[*].*?[*]/)+z^\s*`definer   z^(\s*)(package)(\s+)z^(\s*)(import)(\s+)r   z\nz\s+z\\\nz/(\\\n)?/(\n|(.|\n)*?[^\\]\n)z/(\\\n)?[*](.|\n)*?[*](\\\n)?/z[{}#@]zL?"r   z4L?'(\\.|\\[0-7]{1,3}|\\x[a-fA-F0-9]{1,2}|[^\\\'\n])'z%(\d+\.\d*|\.\d+|\d+)[eE][+-]?\d+[lL]?z(\d+\.\d*|\.\d+|\d+[fF])[fF]?z4([1-9][_0-9]*)?\s*\'[sS]?[bB]\s*[xXzZ?01][_xXzZ?01]*z6([1-9][_0-9]*)?\s*\'[sS]?[oO]\s*[xXzZ?0-7][_xXzZ?0-7]*z6([1-9][_0-9]*)?\s*\'[sS]?[dD]\s*[xXzZ?0-9][_xXzZ?0-9]*zB([1-9][_0-9]*)?\s*\'[sS]?[hH]\s*[xXzZ?0-9a-fA-F][_xXzZ?0-9a-fA-F]*z
\'[01xXzZ]z[0-9][_0-9]*z[~!%^&*+=|?:<>/-])Zinsidedistz\b)r   z[()\[\],.;\'$]z`[a-zA-Z_]\w*)Z	accept_onaliasr   r   r   r   r   assertr   Zassumer   beforer   bindZbinsZbinsofr   r    r!   r"   r#   r$   r%   cellcheckerZclockingr&   config
constraintcontextr(   ZcoverZ
covergroupZ
coverpointZcrossr)   r*   r+   Zdesignr,   r-   r.   r/   r0   r1   Z
endcheckerZendclockingZ	endconfigr2   r3   ZendgroupZendinterfacer4   r5   r6   Z
endprogramZendpropertyZendsequencer7   r8   r9   r:   Z
eventuallyexpectZexportZexternr<   Zfirst_matchr=   r>   Zforeachr?   r@   ZforkjoinrA   rB   rC   globalrD   rE   rF   ZiffZifnoneZignore_binsZillegal_binsZimpliesZ
implementsr   incdirr   rG   rH   rI   instanceZinterconnectZ	interfaceZ	intersectrK   Zjoin_anyZ	join_nonerL   ZletZliblistlibrarylocalrM   rN   matchesrO   ZmodportrP   rQ   rR   ZnettypenewZnexttimerS   rT   ZnoshowcancelledrU   rV   rW   nullrX   rY   packagerZ   r[   r\   r]   r^   priorityprogrampropertyr   r_   r`   ra   rb   Zpulsestyle_ondetectZpulsestyle_oneventpureZrandZrandcZrandcaseZrandsequencerc   rd   Z	reject_onre   rf   Zrestrictrg   rh   ri   rj   rk   rl   Zs_alwaysZs_eventuallyZ
s_nexttimeZs_untilZs_until_withrm   sequenceZshowcancelledro   ZsoftZsolverp   rq   Zstaticstrongrr   rs   rt   superZsync_accept_onZsync_reject_onru   Ztaggedrv   r   Z
throughoutZtimeprecisionZtimeunitrw   rx   ry   r{   unionuniqueZunique0untilZ
until_withZuntypeduser~   Zvirtualr   Z
wait_orderZweakr   r   r   ZwildcardwithZwithinr   r   z(class)(\s+)([a-zA-Z_]\w*)z(extends)(\s+)([a-zA-Z_]\w*)z,(endclass\b)(?:(\s*)(:)(\s*)([a-zA-Z_]\w*))?)!r   r   chandler'   r;   r   rJ   r   r   r   r   r   r   Z	shortrealrn   r   r   rz   r|   r}   r   r   r   r   r   r   r   r   r   r   r   r   Zwor)z	`__FILE__z	`__LINE__z`begin_keywordsz`celldefinez`default_nettypez`definez`elsez`elsifz`end_keywordsz`endcelldefinez`endifz`ifdefz`ifndefz`includez`linez`nounconnected_drivez`pragmaz	`resetallz
`timescalez`unconnected_drivez`undefz`undefineall)z$exitz$finishz$stopz	$realtimez$stimez$timez$printtimescalez$timeformatz$bitstorealz$bitstoshortrealz$castz$itorz$realtobitsz$rtoiz$shortrealtobitsz$signedz	$unsignedz$bitsz$isunboundedz	$typenamez$dimensionsz$highz
$incrementz$leftz$lowz$rightz$sizez$unpacked_dimensionsz$acosz$acoshz$asinz$asinhz$atanz$atan2z$atanhz$ceilz$clog2z$cosz$coshz$expz$floorz$hypotz$lnz$log10z$powz$sinz$sinhz$sqrtz$tanz$tanhz
$countbitsz
$countonesz
$isunknownz$onehotz$onehot0z$infoz$errorz$fatalz$warningz$assertcontrolz$assertfailoffz$assertfailonz$assertkillz$assertnonvacuousonz
$assertoffz	$assertonz$assertpassoffz$assertpassonz$assertvacuousoffz$changedz$changed_gclkz$changing_gclkz$falling_gclkz$fellz
$fell_gclkz$future_gclkz$pastz
$past_gclkz$rising_gclkz$rosez
$rose_gclkz$sampledz$stablez$stable_gclkz$steady_gclkz$coverage_controlz$coverage_getz$coverage_get_maxz$coverage_mergez$coverage_savez$get_coveragez$load_coverage_dbz$set_coverage_db_namez$dist_chi_squarez$dist_erlangz$dist_exponentialz$dist_normalz$dist_poissonz$dist_tz$dist_uniformz$randomz$q_addz$q_examz$q_fullz$q_initializez	$q_removez$async$and$arrayz$async$and$planez$async$nand$arrayz$async$nand$planez$async$nor$arrayz$async$nor$planez$async$or$arrayz$async$or$planez$sync$and$arrayz$sync$and$planez$sync$nand$arrayz$sync$nand$planez$sync$nor$arrayz$sync$nor$planez$sync$or$arrayz$sync$or$planez$systemz$displayz	$displaybz	$displayhz	$displayoz$monitorz	$monitorbz	$monitorhz	$monitoroz$monitoroffz
$monitoronz$strobez$strobebz$strobehz$strobeoz$writez$writebz$writehz$writeoz$fclosez	$fdisplayz
$fdisplaybz
$fdisplayhz
$fdisplayoz$feofz$ferrorz$fflushz$fgetcz$fgetsz	$fmonitorz
$fmonitorbz
$fmonitorhz
$fmonitoroz$fopenz$freadz$fscanfz$fseekz$fstrobez	$fstrobebz	$fstrobehz	$fstrobeoz$ftellz$fwritez$fwritebz$fwritehz$fwriteoz$rewindz$sformatz	$sformatfz$sscanfz$swritez$swritebz$swritehz$swriteoz$ungetcz	$readmembz	$readmemhz
$writemembz
$writememhz$test$plusargsz$value$plusargsz$dumpallz	$dumpfilez
$dumpflushz
$dumplimitz$dumpoffz$dumponz
$dumpportsz$dumpportsallz$dumpportsflushz$dumpportslimitz$dumpportsoffz$dumpportsonz	$dumpvarsz[a-zA-Z_]\w*:(?!:)z\$?[a-zA-Z_]\w*z\\(\S+)r   z#popz/\\([\\abfnrtv"\']|x[a-fA-F0-9]{2,4}|[0-7]{1,3})z	[^\\"\n]+z\\z[^/\n]+z/[*](.|\n)*?[*]/z//.*?\nr   z	(?<=\\)\nz	[\w:]+\*?)r   r   r   r   N)&r   r   r   r   r   r   r   r   r   r	   r   r   r   r   r   r   r   r   r   r   r   r   r   r   r   r   r
   r   Wordr   r   ZDeclarationClassr   r   r   r   r   r   r   r   r   r      s   
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B Zdefdefdefd	ejfd
ejfdefdejfdefdefdeeeejfdeeeefdeeeejefdeeeejfdeejejfedddejfdeeeejfdeeeejeeeejee	fdeejeeefdeeeedfedededdefgeddejfd efd!ed"fged#ddejfged$ddefgd%ejfd&ejfd'ej fd(ej!fd)ej"fd*ej#fgd+Z$d,S )-r   z:
    For VHDL source code.

    .. versionadded:: 1.5
    Zvhdlz*.vhdlz*.vhdztext/x-vhdlz\nz\s+z\\\nz--.*?$z'(U|X|0|1|Z|W|L|H|-)'z[~!%^&*+=|?:<>/-]z
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(end)(\s+)endblocktypeskeywordsnumbersz	[a-z_]\w*z(\s+);z#pop)booleanr   	characterZseverity_levelrJ   r   Zdelay_lengthZnaturalZpositiver   Z
bit_vectorZfile_open_kindZfile_open_statusZ
std_ulogicZstd_ulogic_vectorZ	std_logicZstd_logic_vectorrn   r|   )_absaccessafterr   allr   architecturearrayr   	attributer   blockbodybufferZbusr#   	componentconfigurationZconstantZ
disconnectZdowntor/   r   r0   entityexitfiler=   rA   rB   ZgenericgroupZguardedrF   ZimpureinZinertialrH   islabelr   linkageliteralloopmapmodrQ   r   nextrT   rU   r   ZofonopenrX   Zothersoutr   portZ	postponedZ	procedureprocessr   rangerecordregisterZrejectremrg   ZrolZrorselectZseveritysignalZsharedZslaZsllZsraZsrlsubtypeZthento	transportrz   Zunitsr   r   variabler   whenr   r   r   r   z\d{1,2}#[0-9a-f_]+#?z\d+z(\d+\.\d*|\.\d+|\d+)E[+-]?\d+zX"[0-9a-f_]+"z
O"[0-7_]+"z	B"[01_]+")r   r   r   r   r   N)%r   r   r   r   r   r   r   r   re	MULTILINE
IGNORECASEflagsr   r	   r   r   r   r
   r   	Attributer   r   r   r   r   r   r   r   r   r   r   r   r   r   r   r   r   r   r   r   r   r   w  sp   

)r   r#  Zpygments.lexerr   r   r   r   r   r   Zpygments.tokenr   r	   r
   r   r   r   r   r   __all__r   r   r   r   r   r   r   <module>	   s    (
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